CMOS-Compatible vertical-silicon-nanowire gate-all-around P-Type tunneling FETs with ≤ 5-mV/decade subthreshold swing

IEEE Electron Device Letters

Volumn 32, Issue 11, 2011, Pages 1504-1506

  Gandhi, Ramanathan ^a   Chen, Zhixian ^a   Singh, Navab ^a   Banerjee, Kaustav ^b   Lee, Sungjoo ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b University of California   (United States)

^c Sungkyunkwan University   (South Korea)

Author keywords

CMOS technology; Gate all around (GAA); Steep subthreshold slope; Subthreshold swing (SS); Top down; Tunneling field effect transistor (TFET); Vertical silicon nanowire (SiNW)

Indexed keywords

CMOS TECHNOLOGY; GATE-ALL-AROUND; SUBTHRESHOLD SLOPE; SUBTHRESHOLD SWING; TOPDOWN; TUNNELING FIELD-EFFECT TRANSISTOR (TFET); VERTICAL SILICON NANOWIRE (SINW);

CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; FIELD EFFECT TRANSISTORS; TRANSISTORS;

NANOWIRES;

EID: 80054985576     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2165331     Document Type: Article

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