Small-signal performance and modeling of sub-50 nm nMOSFETs with fT above 460-GHz

Solid-State Electronics

Volumn 52, Issue 6, 2008, Pages 899-908

  Dimitrov, V ^a   Heng, J B ^a   Timp, K ^a   Dimauro, O ^a   Chan, R ^a   Hafez, M ^a   Feng, J ^a   Sorsch, T ^b   Mansfield, W ^b   Miner, J ^b   Kornblit, A ^b   Klemens, F ^b   Bower, J ^b   Cirelli, R ^b   Ferry, E J ^b   Taylor, A ^b   Feng, M ^a   Timp, G ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b New Jersey Nanotechnology Consortium   (United States)

Author keywords

High frequency; Mixed signal; Radio frequency (RF) MOSFET; RF MOSFET modeling

Indexed keywords

CUTOFF FREQUENCY; FREQUENCY BANDS; GATES (TRANSISTOR); SCATTERING PARAMETERS; SUBSTRATES;

MIXED SIGNAL APPLICATIONS; RADIO FREQUENCY (RF) MOSFET DEVICES; RF MOSFET MODELING;

MOSFET DEVICES;

EID: 42749094172     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.01.025     Document Type: Article

References (31)

1. Taylor G.W., and Simmons J.G. Figure of merit for integrated bipolar transistors. Sol State Electron 29 (1986) 941-946
2. Kuhn K., et al. A comparison of state-of-the-art NMOS and HBT devices for analog/mixed-circuit/RF circuit application. VLSI Tech Symp Tech Dig 224 (2004)
3. Momose H.S., Ohguro T., Morifuji E., Sugaya H., Nakamura S., and Iwai H. Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS. IEEE Trans Electron Dev 48 (2001) 1165-1174
4. max, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability. VLSI Tech Symp (2004) 98-99
5. Lee S., Wagner L., Janannathan B., Csutak S., Pekarik J., Zamdmer N., et al. Record RF performance of sub-46 nm Lgate NFETs in microprocessor SOI CMOS technologies. IEDM Tech Dig (2005) 241-244
6. Suemitsu T., Enoki T., Yokoyama H., and Ishii Y. Impact of two-step-recessed gate structure on RF performance of InP-based HEMTs. Electron Lett 34 (1998) 220-222
7. T = 350/300 GHz and gate delay below 3.3 ps. IEDM Tech Dig (2004) 247-250
8. CEO > 2 V. IEDM Tech Dig (2004) 549-552
9. max. IEDM Tech Dig (2004) 553-556
10. max of 687 GHz. IEDM Tech Dig (2004) 557-560
11. Razavi B., Yan R., and Lee K.F. Impact of distributed gate resistance on the performance of MOS devices. IEEE Trans Circuit Syst-I 41 (1994) 750-754
12. Tiemeijer L.F., et al. Record RF performance of 90 nm CMOS technology. IEDM Tech Dig (2004) 441-444
13. Dambrine G., et al. What are the limiting parameters of deep-submicron MOSFETS for high frequency applications?. IEEE Elec Dev Lett 24 (2003) 189-191
14. Liu W., Gharpurey R., Chang M.C., Erdogan U., Aggarwal R., and Mattia J.P. RF MOSFET modeling ac-counting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model. IEDM Tech Dig (1997) 309-312
15. Pehlke D.R., Schroter M., Burstein A., Matloubian M., and Chang M.F. High-frequency application of MOS compact models and their development for scalable RF MOS libraries. Proc IEEE Custom IC Conf (1998) 219-222
16. Ou J.-J., Jin X., Ma I., Hu C., and Gray P. CMOS RF modeling for GHz communication IC's. VLSI Technol Symp (1998) 94-95
17. Jen SH, Enz C, Pehlke DR, Schroter M, Sheu BJ, Accurate MOS transistor modeling and parameter extraction valid up to 10-GHz. In: Proceedings of European solid-state device research conference Bordeaux, France; 1998. p. 484-7.
18. Cheng Y., et al. RF modeling issues of deep-submicron MOS-FET's for circuit design. Proc IEEE Int Conf Solid-State IC Tech (1998) 416-419
19. Tsividis Y.P. Operation and modeling of the MOS transistor (1987), McGraw-Hill
20. Enz C. An MOS transistor model for RF IC design valid in all regions of operation. IEEE Trans Microw Theory Techn 50 (2002) 342-358
21. Cho D., Kang S., Kim K., and Lee S. An accurate intrinsic capacitance modeling for deep submicrometer MOSFETs. IEEE Trans Electron Dev 42 (1995) 540-548
22. Cheng Y., Chen C., Matloubian M.., and Deen M.J. High-frequency small signal ac and noise modeling of MOSFETs for IC design. IEEE Trans Electron Dev 49 (2002) 400-408
23. Enz C.C., and Cheng Y. MOS transistor modeling for RF IC design. IEEE J Solid-State Circ 35 (2001) 186-201
24. Eminente S., Alessandrini M., and Fiegna C. Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation. Solid-State Electron 48 4 (2004) 543-549
25. Kwon I., Je M., Lee K., and Shin H. A simple and analytical parameter-extraction method of a microwave MOSFET. IEEE Trans Microw Theory Tech 50 (2002) 1503-1509
26. Raskin J.P., Gilon R., Dambrine G., Chen J., Vanhoenacker D., and Colinge J.P. Accurate characterization of SOI MOSFETs for the design of low-voltage, low-power RF ICs. Analog IC Signal Proc 25 (2000) 133-155
27. Goffioul M, Vanhoenacker D, Raskin J-P. Direct extraction techniques of microwave small-signal model and technology parameters for subquarter micron SOI MOSFETs. 5th Symp Diagn Yield 2000:8.
28. Dehan M., Raskin J.-P., and Vanhoenacker D. Comparison of different extraction methods of small-signal parameters for SOI MOSFETs. Proc 32th Eur Microw Conf (2002)
29. Heuermann H., and Schiek B. Robust algorithms for TAN network analyzer self-calibration procedures. IEEE Trans Instrum Meas 43 1 (1994) 18-22
30. Dimitrov V., et al. High performance, sub-50 nm MOSFETS for mixed signal applications. IEDM Tech Dig (2005) 213-216
31. Litwin A. Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors. IEEE Trans Electron Dev 48 9 (2001) 2179-2181