Physical modeling of lateral scaling in bipolar transistors

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 10, 1996, Pages 1484-1492

  Schröter, Michael ^a,b,c,d   Walkey, David J ^a,b,c,e  

^a IEEE

^b NORTEL NETWORKS   (Canada)

^c CARLETON UNIVERSITY   (Canada)

^d Rockwell Semiconductor Systems   (United States)

^e UNIVERSITY OF CALGARY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT DENSITY; ELECTRIC CURRENTS; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; THREE DIMENSIONAL;

PERIMETER TO AREA RATIOS; THREE DIMENSIONAL DEVICE SIMULATION; TWO DIMENSIONAL DEVICE SIMULATION;

BIPOLAR TRANSISTORS;

EID: 0030270763     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.540059     Document Type: Article

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