Power and area optimization for run-time reconfiguration system on programmable chip based on magnetic random access memory

IEEE Transactions on Magnetics

Volumn 45, Issue 2, 2009, Pages 776-780

  Zhao, Weisheng ^a,b   Belhaire, Eric ^a,b   Chappert, Claude ^a,b   Mazoyer, Pascale ^c  

^a CNRS   (France)

^b UNIVERSITÉ PARIS SACLAY   (France)

^c STMICROELECTRONICS   (France)

Author keywords

Flip flop; FPGA; Low power and low die area; LUT; MRAM; Nonvolatile; Run time reconfiguration; SOPC

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLIP FLOP CIRCUITS; MAGNETIC RECORDING; MAGNETISM; MRAM DEVICES; RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE; STANDBY POWER SYSTEMS; TUNNEL JUNCTIONS;

DIE AREA; MRAM; NON-VOLATILE; RUN TIME RECONFIGURATION; SOPC;

MAGNETIC STORAGE;

EID: 60449095985     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2008.2006872     Document Type: Article

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