A compact model of domain wall propagation for logic and memory design

Journal of Applied Physics

Volumn 109, Issue 7, 2011, Pages

  Zhao, W S ^a,b   Duval, J ^a,b   Ravelosona, D ^a,b   Klein, J O ^a,b   Kim, J V ^a,b   Chappert, C ^a,b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CMOS DESIGN; COMPACT MODEL; CURRENT-DRIVEN; DOMAIN WALL MOTION; DOMAIN-WALL PROPAGATION; FREE LAYERS; HIGH-DENSITY; HIGH-SPEED CIRCUITS; LOW POWER; MAGNETIC STRIPES; MAGNETIC TUNNEL JUNCTION; MEMORY APPLICATIONS; MEMORY DESIGN; NANOPILLAR; NON-VOLATILE; SHIFTING SCHEME; SPIN TRANSFER TORQUE; SPINTRONICS; STORAGE ELEMENTS; TUNNEL RESISTANCE; WRITING PROCESS;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FLEXIBLE STRUCTURES; INTEGRATED CIRCUIT MANUFACTURE; MAGNETIC STORAGE; MAGNETIZATION REVERSAL; SHIFT REGISTERS; TUNNEL JUNCTIONS;

MAGNETIC DOMAINS;

EID: 79955408773     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3536793     Document Type: Conference Paper

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