The impulse memory controller

IEEE Transactions on Computers

Volumn 50, Issue 11, 2001, Pages 1117-1132

  Zhang, L ^a   Fang, Z ^a   Parker, M ^a   Mathew, B K ^a   Schaelicke, L ^a   Carter, J B ^a   Hsieh, W C ^a   McKee, S A ^a  

^a University of Utah   (United States)

Author keywords

Computer architecture; Memory systems

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; CONTROL EQUIPMENT; DATA STRUCTURES; MICROPROCESSOR CHIPS; OPTIMIZATION; VECTORS;

IMPULSE MEMORY CONTROLLERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035510702     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.966490     Document Type: Article

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