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Journal of the Electrochemical Society

Volumn 158, Issue 10, 2011, Pages

Scanning tunneling microscopy study of the multi-step deposited and annealed HfSiOx gate dielectric

(6) Yew, K S a Ang, D S a Tang, L J b Cui, K a Bersuker, G c Lysaght, P S c

a NANYANG TECHNOLOGICAL UNIVERSITY (Singapore)

b INSTITUTE OF MICROELECTRONICS (Singapore)

c SEMATECH (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION PROCESS; ELECTRICAL AND RELIABILITY CHARACTERISTICS; ELECTRICAL CHARACTERISTIC; ELECTRICAL STRESS; HIGH TEMPERATURE; HIGH-K GATE DIELECTRICS; LOW RESISTANCE; METAL-OXIDE-SEMICONDUCTOR CAPACITORS; MULTI-STEP; NANOCRYSTALLINES; PHYSICAL THICKNESS; POLYCRYSTALLINE PHASE; SINGLE-STEP; ULTRAHIGH-VACUUM SCANNING TUNNELING MICROSCOPY;

DIELECTRIC DEVICES; DIELECTRIC MATERIALS; GATES (TRANSISTOR); GRAIN BOUNDARIES; SCANNING TUNNELING MICROSCOPY;

GATE DIELECTRICS;

EID: 80052093711 PISSN: 00134651 EISSN: None Source Type: Journal
DOI: 10.1149/1.3622344 Document Type: Article

Times cited : (9)

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