Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

IET Computers and Digital Techniques

Volumn 3, Issue 5, 2009, Pages 476-486

  Raik, J ^a   Govind, V ^a   Ubar, R ^a  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL UNIT; FAULTY LINKS; FUNCTIONAL FAULT MODEL; LOGIC BUILT-IN SELF TEST; NETWORK SWITCHES; NETWORK-ON-A-CHIP; NEW CONCEPT; NUMBER OF SWITCHES; REGULAR MESHES; STRUCTURAL FAULTS; SUPPORT TESTING; TEST CONFIGURATIONS; TEST COVERAGE; TEST PATTERN;

DESIGN FOR TESTABILITY; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT TESTING; SWITCHES; SWITCHING NETWORKS;

BUILT-IN SELF TEST;

EID: 68849118753     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0096     Document Type: Article

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