Impact analysis of performance faults in modern microprocessors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 91-96

  Karimi, Naghmeh ^a   Maniatakos, Michail ^b   Tirumurti, Chandra ^c   Jas, Abhijit ^c   Makris, Yiorgos ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b YALE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL FEATURES; BRANCH PREDICTION; FAULT SIMULATION; IMPACT ANALYSIS; IMPACT PERFORMANCE; IMPROVING PERFORMANCE; MODERN MICROPROCESSOR; OUT OF ORDER; PERFORMANCE IMPACT; PERFORMANCE LOSS RECOVERY; SPECULATIVE EXECUTION; SUPERSCALAR; YIELD ENHANCEMENT;

COMPUTER HARDWARE;

MICROPROCESSOR CHIPS;

EID: 77951017726     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413171     Document Type: Conference Paper

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