A hyper optimal encoding scheme for self-checking circuits

IEEE Transactions on Computers

Volumn 45, Issue 9, 1996, Pages 1022-1030

  Lo, Jien Chung ^a,b  

^a IEEE

^b The University of Rhode Island   (United States)

Author keywords

Concurrent error detection; Logic circuit synthesis; Output encoding; Self checking circuits; Unordered codes

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER HARDWARE; DECODING; DETECTOR CIRCUITS; ENCODING (SYMBOLS); ERROR DETECTION; LOGIC DESIGN; OPTIMIZATION; REDUNDANCY;

BERGER CODES; CHECK BITS; CONCURRENT ERROR DETECTION; HYPER OPTIMAL ENCODING SCHEME; LOGIC CIRCUIT SYNTHESIS; OUTPUT ENCODING; SELF CHECKING CIRCUITS; UNORDERED CODES;

LOGIC CIRCUITS;

EID: 0030246561     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.537125     Document Type: Article

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