Instruction-level impact comparison of RT- vs. gate-level faults in a modern microprocessor controller

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 9-14

  Maniatakos, Michail ^a   Karimi, Naghmeh ^b   Tirumurti, Chandra ^c   Jas, Abhijit ^c   Makris, Yiorgos ^a  

^a Yale University   (United States)

^b UNIVERSITY OF TEHRAN   (Iran)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATIVE STUDIES; CONTROL LOGIC; FAULT SIMULATION; INSTRUCTION-LEVEL; MODERN MICROPROCESSOR; RELATIVE IMPORTANCE;

EMBEDDED SYSTEMS; ERROR CORRECTION; ERROR DETECTION;

MICROPROCESSOR CHIPS;

EID: 70350376748     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.32     Document Type: Conference Paper

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