Design and evaluation of a timestamp-based concurrent error detection method (CED) in a modern microprocessor controller

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2008, Pages 454-462

  Maniatakos, Michail ^a   Karimi, Naghmeh ^b   Makris, Yiorgos ^a   Jas, Abhijit ^c   Tirumurti, Chandra ^c  

^a YALE UNIVERSITY   (United States)

^b UNIVERSITY OF TEHRAN   (Iran)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT ERROR DETECTION; CONTROL LOGIC; DETECTION LATENCY; EXECUTION TIME; LOW LATENCY; MODERN MICROPROCESSOR; NORMAL OPERATIONS; OUT OF ORDER; SUPERSCALAR; TIME-STAMP;

CONCURRENCY CONTROL; CONTROLLERS; CONVOLUTIONAL CODES; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PROBABILITY DENSITY FUNCTION; QUALITY ASSURANCE;

FAULT TOLERANCE;

EID: 67649994693     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2008.59     Document Type: Conference Paper

References (21)

1. M. Goessel, and S. Graf, Error Detection Circuits, McGraw-Hill, 1993.
2. S. Mitra, and E. J. McCluskey, "Which Concurrent Error Detection Scheme to Choose?" in Proc. of the International Test Conference, 2000, pp. 985-994.
3. A. Avizienis, and J. P. J. Kelly, "Fault Tolerance by Design Diversity: Concepts and Experiments", IEEE Transactions on Computers, vol.17, no.8, pp. 67-80, 1984.
4. K. Mohanram, and N. A. Touba, "Cost-Effective Approach for Reducing Soft Error Rate in Logic Circuits," in Proc. of the International Test Conference, 2003, pp. 893-901.
5. G. Aksenova, and E. Sogomonyan, "Design of Self-Checking Built-in Check Circuits for Automata with Memory," Automation and Remote Control, vol.36, no.7, pp. 1169-1177, 1975.
6. S. Dhawan, and R. C. D. Vries, "Design of Self-Checking Sequential Machines," IEEE Transactions on Computers, vol.37, no.10, 1988, pp. 1280-1284.
7. C. Zeng, N. Saxena, and E.J. McCluskey, "Finite State Machine Synthesis with Concurrent Error Detection," in Proc. of the International Test Conference, 1998, pp. 672-679.
8. D. Das, and N. A. Touba, "Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes," Journal of Electronic Testing: Theory and Applications, vol.15, no.2, 1999, pp. 145-155. (Pubitemid 30522301)
9. N. K. Jha and S.-J. Wang, "Design and Synthesis of Self-Checking VLSI Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.12, no.6, 1993, pp. 878-887. (Pubitemid 23690187)
10. R. A. Parekhji, G. Venkatesh, and S. D. Sherlekar, "Concurrent Error Detection Using Monitoring Machines," IEEE Design and Test of Computers, vol.12, no.3, 1995, pp. 24-32.
11. S. Almukhaizim, P. Drineas, and Y. Makris, "Entropy-Driven Parity-Tree Selection for Low-Overhead Concurrent Error Detection in Finite State Machines," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, no.8, 2006, pp. 1547-1554. (Pubitemid 44144038)
12. S. Almukhaizim, P. Drineas, and Y. Makris, "On Concurrent Error Detection with Bounded Latency in FSMs in Proc. of the IEEE Design Automation and Test in Europe Conference (DATE), 2004, pp. 596-601.
13. R. Vemu, A. Jas, J. A. Abraham, S. Patil, and R. Galivanche, "Low-Cost Concurrent Error Detection Technique for Processor Control Logic," in Proc. of Design Automation and Test in Europe, 2008, pp. 897-902.
14. Y. Makris, I. Bayraktaroglu, and A. Orailoglu, "Enhancing Reliability of RTL Controller-Datapath Circuits via Invariant-Based Concurrent Test," IEEE Transactions on Reliability, vol.53, no.2, 2004, pp. 269-278.
15. A. Mahmood, and E. J. McCluskey, "Concurrent Error Detection Using Watchdog Processors-A Survey", IEEE Transactions on Computers, vol.37, no.2, 1988, pp. 160-174. (Pubitemid 18596597)
16. A. Mendelson, and N. Suri, "Designing High-Performance and Reliable Superscalar Architectures-the Out of Order Reliable Superscalar (O3RS) Approach", In Proc. of International Conference on Dependable Systems and Networks, 2000, pp. 25-28.
17. A. K. Somani, and J. Nickel, "REESE: a Method of Soft Error Detection in Microprocessors", in Proc. of International Conference on Dependable Systems and Networks, 2001, pp.401-410.
18. N. J. Wang, J. Quek, T. M. Rafacz, S. J. Patel, "Characterizing the Effect of Transient Faults on a High-Performance Processor Pipeline", in Proc. of International Conference on Dependable Systems and Networks, Florence, Italy, 2004, pp.61-70.
19. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," In Proc. of International. Symposium on Microarchitecture, 2003, pp. 29-40.
20. N. Karimi, M. Maniatakos, A. Jas, and Y. Makris, "On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors," in Proc. of International Test Conference, 2008.
21. J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufmann Publishers, 2003.