Novel adhesive development for CMOS-compatible thin wafer handling

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1239-1244

  Tamura, K ^a   Nakada, K ^a   Taneichi, N ^a   Andry, P ^b   Knickerbocker, J ^b   Rosenthal, C ^c  

^a TOKYO OHKA KOGYO CO LTD   (Japan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c Tokyo Ohka Kogyo America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CMOS COMPATIBLE; CU DAMASCENE; DEBONDING PROCESS; FORM FACTORS; FORMATION PROCESS; GLASS CARRIER; GLASS TRANSITION POINTS; HIGH TEMPERATURE; HIGHER TEMPERATURES; INSULATING FILM; LOW PROCESS TEMPERATURE; LOW STRESS; MICRO AND MACRO; NOVEL ADHESIVES; OUT-GASSING; PLANARITY; POWER EFFICIENCY; PROCESS INTEGRATION; PROCESSING TEMPERATURE; SELECTION PROCESS; SOFTENING POINTS; SOLDER REFLOW; TEMPERATURE TOLERANCE; THERMAL BUDGET; THERMAL STABILITY; THIN FILM INSULATORS; THIN WAFERS; THROUGH-SILICON-VIA; WAFERBONDING TECHNOLOGY; WARPAGES;

ADHESIVES; APPROXIMATION THEORY; DEBONDING; DISSOLUTION; FITS AND TOLERANCES; GLASS; GLASS BONDING; GLASS TRANSITION; PROCESSING; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 77955199007     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490859     Document Type: Conference Paper

References (9)

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