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Electronics System Integration Technology Conference, ESTC 2010 - Proceedings

Volumn , Issue , 2010, Pages

Thin wafer processing and chip stacking for 3D integration

(4) Matthias, T a Kim, B b Wimplinger, M a Lindner, P a

a EV GROUP (Austria)

b EV Group Inc (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3-D INTERCONNECTS; 300 MM WAFERS; ALIGNMENT ACCURACY; BOND INTERFACE; BUILDING BLOCKES; CARRIER WAFERS; CHIP STACKING; COST OF OWNERSHIP; CYCLE TIME; DEVICE WAFERS; DICING TAPES; ELECTRICAL CONNECTION; FUSION BONDING; HIGH DENSITY; INTEGRATION SCHEME; KEY TECHNOLOGIES; MANUFACTURABILITY; MATERIALS AND PROCESS; METAL-METAL BONDING; PROCESS IMPROVEMENT; PROCESS LINE; PROCESS STEPS; REAL ESTATE CONSUMPTION; SINGULATION; SUBMICRON; TECHNICAL FEASIBILITY; THERMO-COMPRESSION; THIN WAFERS; THROUGH SILICON VIAS; TOTAL THICKNESS VARIATIONS; WAFER STACKING; WAFER THICKNESS;

ALIGNMENT; ASPECT RATIO; COST REDUCTION; DEBONDING; ELECTRIC CONNECTORS; INTEGRATION; LITHOGRAPHY; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 78651296228 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ESTC.2010.5642873 Document Type: Conference Paper

Times cited : (10)

References (8)

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3
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4
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5
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6
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- Effects of bonding process parameters on the interfacial properties of Cu-Cu direct bonds for TSV integration
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7
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8
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