Optimization of chemistry and process parameters for void-free copper electroplating of high aspect ratio through-silicon vias for 3D integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1301-1306

  Malta, Dean ^a   Gregory, Christopher ^a   Temple, Dorota ^a   Wang, Chen ^b   Richardson, Thomas ^b   Zhang, Yun ^b  

^a RTI INTERNATIONAL   (United States)

^b Enthone Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; COMPONENT LEVELS; COPPER ELECTROPLATING; ELECTRONIC SYSTEMS; HIGH ASPECT RATIO; KEY ELEMENTS; LARGE DIAMETER; PLATING SOLUTIONS; PRE-TREATMENTS; PROCESS DEVELOPMENT; PROCESS PARAMETERS; SEED LAYER; THROUGH SILICON VIAS; VOID-FREE;

COPPER; COPPER PLATING; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS; PRESSURE DROP; TECHNOLOGY; THREE DIMENSIONAL;

ASPECT RATIO;

EID: 70349655245     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074179     Document Type: Conference Paper

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