Electrical demonstration of TSV interconnects and multilevel metallization for 3D Si interposer applications

43rd International Symposium on Microelectronics 2010, IMAPS 2010

Volumn , Issue , 2010, Pages 7-14

  Vick, Erik ^a   Goodwin, Scott ^a   Temple, Dorota ^a  

^a RTI INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACKSIDE METAL; DUAL DAMASCENE; DUAL DAMASCENE PROCESS; FUNCTIONAL TESTING; MULTILEVEL METALLIZATION; OPTIMUM PROCESS CONDITIONS; PROCESS CONDITION; TARGET APPLICATION;

ASPECT RATIO; AUTOMOBILE MANUFACTURE; FABRICATION; METALS; MICROELECTRONICS; SILICON WAFERS; THREE DIMENSIONAL COMPUTER GRAPHICS;

DEMONSTRATIONS;

EID: 78651469386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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