A 4-kb low-power SRAM design with negative word-line scheme

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 5, 2007, Pages 1069-1076

  Wang, Chua Chin ^a   Lee, Ching Li ^a   Lin, Wun Ji ^b  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b Terax Communication Technology Inc   (Taiwan)

Author keywords

4 T SRAM cell; Leakage current; Negative word line (NWL); Power delay product; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; STANDBY POWER SYSTEMS; TRANSISTORS;

CELL ACCESS TRANSISTORS; NEGATIVE WORD-LINE (NWL); POWER-DELAY PRODUCT; SRAM DESIGN; STANDBY POWER CONSUMPTION;

STATIC RANDOM ACCESS STORAGE;

EID: 34248673198     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.888767     Document Type: Article

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