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Volumn , Issue , 2007, Pages 1289-1292

A novel 8T SRAM cell with improved read-SNM

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL LENGTHS; CHANNEL REGIONS; DEVICE GEOMETRIES; DOPANT FLUCTUATIONS; FUTURE TECHNOLOGIES; READ OPERATIONS; SCALING-DOWN; SRAM CELLS; SRAM STABILITY;

EID: 50049099491     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2007.4488015     Document Type: Conference Paper
Times cited : (27)

References (10)
  • 1
    • 0035308547 scopus 로고    scopus 로고
    • A. Bhavnagarwala, X. Tang, and J. Meindl. The impact of intrinsic device fluctuations on CMOS SRAM cell stability, Solid-State Circuits, IEEE Journal of, 2001. 36, 658-665
    • A. Bhavnagarwala, X. Tang, and J. Meindl. "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", Solid-State Circuits, IEEE Journal of, 2001. 36, 658-665
  • 2
    • 33746369469 scopus 로고    scopus 로고
    • B. Calhoun and Chandrakasan, A.Static noise margin variation for subthreshold SRAM in 65-nm CMOS. Solid-State Circuits, IEEE Journal of. 2006, 41, 1673-1679
    • B. Calhoun and Chandrakasan, "A.Static noise margin variation for subthreshold SRAM in 65-nm CMOS". Solid-State Circuits, IEEE Journal of. 2006, 41, 1673-1679
  • 3
    • 34547298101 scopus 로고    scopus 로고
    • Y. Ye, M. Khellah, D. Somasekhar and V. De. Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches, Circuits and Systems. 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, 4pp.
    • Y. Ye, M. Khellah, D. Somasekhar and V. De. "Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches", Circuits and Systems. 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, 4pp.
  • 7
    • 0023437909 scopus 로고    scopus 로고
    • E. Seevink and F. List, Static Noise Margin Analysis of MOS SRAM Cells, Solid-State Circuits, IEEE Journal of, 1987, 5, 748-754
    • E. Seevink and F. List, "Static Noise Margin Analysis of MOS SRAM Cells", Solid-State Circuits, IEEE Journal of, 1987, 5, 748-754
  • 8
    • 17644390667 scopus 로고    scopus 로고
    • A high density, low leakage, 5T SRAM for embedded caches Solid-State Circuits Conference, 2004. ESSCIRC 2004
    • Carlson, I. , Andersson, S. , Natarajan, S. and Alvandpour, A. "A high density, low leakage, 5T SRAM for embedded caches" Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 2004, 215-218
    • (2004) Proceeding of the 30th European , pp. 215-218
    • Carlson, I.1    Andersson, S.2    Natarajan, S.3    Alvandpour, A.4
  • 9
    • 31344473488 scopus 로고    scopus 로고
    • Takeda, K.. Hagihara. Y., Aimoto, Y., Nomura, M., Nakazawa, Y., Ishii, T. and Kobatake. H. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications,Solid-State Circuits, IEEE Journal of, 2006, 41. 113-121
    • Takeda, K.. Hagihara. Y., Aimoto, Y., Nomura, M., Nakazawa, Y., Ishii, T. and Kobatake. H. "A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications",Solid-State Circuits, IEEE Journal of, 2006, 41. 113-121
  • 10
    • 34247367942 scopus 로고    scopus 로고
    • Aly, R. E.,Bayoumi, M. A. Low-Power Cache Design Using 7T SRAM Cell Circuit and Systems Il, IEEE Transaction on, April 2007, 318-322
    • Aly, R. E.,Bayoumi, M. A. "Low-Power Cache Design Using 7T SRAM Cell " Circuit and Systems Il, IEEE Transaction on, April 2007, 318-322


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.