-
2
-
-
67650373442
-
0.25As MOSFET
-
Jul.
-
0.25As MOSFET", IEEE Electron Device Lett., vol. 30, no. 7, pp. 700-702, Jul. 2009.
-
(2009)
IEEE Electron. Device Lett.
, vol.30
, Issue.7
, pp. 700-702
-
-
Wu, Y.Q.1
Wang, W.K.2
Koybasi, O.3
Zakharov, D.N.4
Stach, E.A.5
Nakahara, S.6
Hwang, J.C.M.7
Ye, P.D.8
-
3
-
-
77952345218
-
Highperformance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/μm: New HBr pretreatment and channel engineering
-
Y. Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. D. Ye, "Highperformance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/μm: New HBr pretreatment and channel engineering", in IEDM Tech. Dig., 2009, pp. 296-299.
-
(2009)
IEDM Tech. Dig.
, pp. 296-299
-
-
Wu, Y.Q.1
Xu, M.2
Wang, R.S.3
Koybasi, O.4
Ye, P.D.5
-
4
-
-
54849375000
-
Carrier transport in highmobility III-V quantum-well transistor and performance impact for highspeed low-power logic applications
-
Oct.
-
G. Dewey, M. K. Hudait, K. Lee, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit, and R. Chau, "Carrier transport in highmobility III-V quantum-well transistor and performance impact for highspeed low-power logic applications", IEEE Electron Device Lett., vol. 29, no. 10, pp. 1094-1097, Oct. 2008.
-
(2008)
IEEE Electron. Device Lett.
, vol.29
, Issue.10
, pp. 1094-1097
-
-
Dewey, G.1
Hudait, M.K.2
Lee, K.3
Pillarisetty, R.4
Rachmady, W.5
Radosavljevic, M.6
Rakshit, T.7
Chau, R.8
-
5
-
-
79951817457
-
Logic performance evaluation and transport physics of Schottky-gate III-V compound semiconductor quantum well field effect transistors for power supply voltages (Vcc) raning from 0.5 V to 1.0 V
-
G. Dewey, R. Kotlyar, R. Pillarisetty, M. Radosavljevic, T. Rakshit, H. Then, and R. Chau, "Logic performance evaluation and transport physics of Schottky-gate III-V compound semiconductor quantum well field effect transistors for power supply voltages (Vcc) raning from 0.5 V to 1.0 V", in IEDM Tech. Dig., 2009, pp. 452-455.
-
(2009)
IEDM Tech. Dig.
, pp. 452-455
-
-
Dewey, G.1
Kotlyar, R.2
Pillarisetty, R.3
Radosavljevic, M.4
Rakshit, T.5
Then, H.6
Chau, R.7
-
6
-
-
48649096271
-
Logic performance of 40 nm InAs HEMTs
-
D. H. Kim and J. A. Del Alamo, "Logic performance of 40 nm InAs HEMTs", in IEDM Tech. Dig., 2007, pp. 629-632.
-
(2007)
IEDM Tech. Dig.
, pp. 629-632
-
-
Kim, D.H.1
Del Alamo, J.A.2
-
7
-
-
64549115313
-
30 nm E-mode InAs pHEMTs for THz and future logic applications
-
D. H. Kim and J. A. Del Alamo, "30 nm E-mode InAs pHEMTs for THz and future logic applications", in IEDM Tech. Dig., 2008, pp. 719-722.
-
(2008)
IEDM Tech. Dig.
, pp. 719-722
-
-
Kim, D.H.1
Del Alamo, J.A.2
-
8
-
-
64549119005
-
Full-band and atomistic simulation of realistic 40 nm InAs HEMT
-
M. Luisier, N. Neophytou, N. Kharche, and G. Klimeck, "Full-band and atomistic simulation of realistic 40 nm InAs HEMT", in IEDM Tech. Dig., 2008, pp. 887-890.
-
(2008)
IEDM Tech. Dig.
, pp. 887-890
-
-
Luisier, M.1
Neophytou, N.2
Kharche, N.3
Klimeck, G.4
-
9
-
-
67650100004
-
Performance analysis of 60-nm gate-length III-V InGaAs HEMTs: Simulations versus experiments
-
Jul.
-
N. Neophytou, T. Rakshit, and M. S. Lundstrom, "Performance analysis of 60-nm gate-length III-V InGaAs HEMTs: Simulations versus experiments", IEEE Trans. Electron Devices, vol. 56, no. 7, pp. 1377-1387, Jul. 2009.
-
(2009)
IEEE Trans. Electron. Devices
, vol.56
, Issue.7
, pp. 1377-1387
-
-
Neophytou, N.1
Rakshit, T.2
Lundstrom, M.S.3
-
10
-
-
77952324482
-
Performance analysis of ultra-scaled InAs HEMTs
-
N. Kharche, G. Klimeck, D. H. Kim, J. A. Del Alamo, and M. Luisier, "Performance analysis of ultra-scaled InAs HEMTs", in IEDM Tech. Dig., 2009, pp. 456-459.
-
(2009)
IEDM Tech. Dig.
, pp. 456-459
-
-
Kharche, N.1
Klimeck, G.2
Kim, D.H.3
Del Alamo, J.A.4
Luisier, M.5
-
11
-
-
79957655366
-
Device physics and performance potential of III-V field effect transistors
-
New York: Springer-Verlag
-
Y. Liu, H. S. Pal, M. S. Lundstrom, D. H. Kim, J. A. Del Alamo, and D. A. Antoniadis, "Device physics and performance potential of III-V Field Effect Transistors", in Fundamentals of III-V Semiconductor MOSFETs. New York: Springer-Verlag, 2010, pp. 31-49.
-
(2010)
Fundamentals of III-V Semiconductor MOSFETs
, pp. 31-49
-
-
Liu, Y.1
Pal, H.S.2
Lundstrom, M.S.3
Kim, D.H.4
Del Alamo, J.A.5
Antoniadis, D.A.6
-
12
-
-
70349498304
-
Scalability of sub-100 nm thin channl InAs PHEMTs
-
D. H. Kim and J. A. Del Alamo, "Scalability of sub-100 nm thin channl InAs PHEMTs", in Proc. IEEE IPRM, 2009, pp. 132-135.
-
(2009)
Proc. IEEE IPRM
, pp. 132-135
-
-
Kim, D.H.1
Del Alamo, J.A.2
-
13
-
-
77149125593
-
Simulation of III-V HEMTs for high-speed low-power logic applications
-
May
-
Y. Liu and M. S. Lundstrom, "Simulation of III-V HEMTs for high-speed low-power logic applications", ECS Trans., vol. 19, no. 5, pp. 331-342, May 2009.
-
(2009)
ECS Trans.
, vol.19
, Issue.5
, pp. 331-342
-
-
Liu, Y.1
Lundstrom, M.S.2
-
14
-
-
41749098089
-
Atomistic simulation of realistically sized nanodevices using NEMO 3-D - Part I: Models and benchmarks
-
DOI 10.1109/TED.2007.902879
-
G. Klimeck, S. S. Ahmed, H. Bae, N. Kharche, R. Rahman, S. Clark, B. Haley, S. H. Lee, M. Naumov, H. Ryu, F. Saied, M. Prada, M. Korkusinski, and T. B. Boykin, "Atomistic simulation of realistically sized nanosevices using NEMO 3-D-Part I: Models and benchmarks", IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2079-2089, Sep. 2007. (Pubitemid 351485729)
-
(2007)
IEEE Transactions on Electron Devices
, vol.54
, Issue.9
, pp. 2079-2089
-
-
Klimeck, G.1
Ahmed, S.S.2
Bae, H.3
Clark, S.4
Haley, B.5
Lee, S.6
Naumov, M.7
Ryu, H.8
Saied, F.9
Prada, M.10
Korkusinski, M.11
Boykin, T.B.12
Rahman, R.13
-
15
-
-
48649099805
-
30-nm InAs pseudomorphic HEMTs on an InP substrate with a current-gain cutoff frequency of 628 GHz
-
Aug.
-
D. H. Kim and J. A. Del Alamo, "30-nm InAs pseudomorphic HEMTs on an InP substrate with a current-gain cutoff frequency of 628 GHz", IEEE Electron Device Lett., vol. 29, no. 8, pp. 830-833, Aug. 2008.
-
(2008)
IEEE Electron. Device Lett.
, vol.29
, Issue.8
, pp. 830-833
-
-
Kim, D.H.1
Del Alamo, J.A.2
-
16
-
-
73349091811
-
A self-aligned InGaAs HEMT architecture for logic applications
-
Jan.
-
N. Waldron, D. H. Kim, and J. A. Del Alamo, "A self-aligned InGaAs HEMT architecture for logic applications", IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 297-304, Jan. 2010.
-
(2010)
IEEE Trans. Electron. Devices
, vol.57
, Issue.1
, pp. 297-304
-
-
Waldron, N.1
Kim, D.H.2
Del Alamo, J.A.3
-
17
-
-
79957646659
-
-
private communication
-
D. H. Kim, private communication, 2010.
-
(2010)
-
-
Kim, D.H.1
-
19
-
-
79957657243
-
-
Ph. D. dissertation, Purdue Univ., West Lafayette, IN
-
H. S. Pal, "Device physics studies of III-V and silicon MOSFETs for digital logic", Ph. D. dissertation, Purdue Univ., West Lafayette, IN, 2010.
-
(2010)
Device Physics Studies of III-V and Silicon MOSFETs for Digital Logic
-
-
Pal, H.S.1
|