A self-aligned InGaAs HEMT architecture for logic applications

IEEE Transactions on Electron Devices

Volumn 57, Issue 1, 2010, Pages 297-304

  Waldron, Niamh ^a,b   Kim, Dae Hyun ^a   Del Alamo, Jesús A ^a  

^a USA   (United States)

^b IMEC   (Belgium)

Author keywords

Contact resistance; FET logic devices; HEMT

Indexed keywords

BARRIER RESISTANCE; CURRENT TECHNOLOGY; DEVICE ARCHITECTURES; ENHANCEMENT MODES; ENHANCEMENT-MODE; FET LOGIC; FET LOGIC DEVICES; GATE-LEAKAGE CURRENT; GATE-LENGTH; HIGH-K GATE DIELECTRICS; LOGIC APPLICATIONS; ORDERS OF MAGNITUDE; RESISTANCE VALUES; SCALING CAPABILITY; SELF ALIGNED PROCESS; SELF-ALIGNED; SOURCE RESISTANCE; TEST STRUCTURE; TRILAYERS;

CONTACT RESISTANCE; GATE DIELECTRICS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC DEVICES; MESFET DEVICES; SEMICONDUCTING INDIUM;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 73349091811     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2035031     Document Type: Article

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