메뉴 건너뛰기




Volumn , Issue , 2011, Pages 607-612

Flow-based partitioning and position constraints in VLSI placement

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL VIEW; PARTITIONING-BASED PLACEMENT; POLYNOMIAL-TIME; RUNTIMES; VLSI PLACEMENT;

EID: 79957568451     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (28)
  • 4
    • 46449101715 scopus 로고    scopus 로고
    • A faster polynomial algorithm for the unbalanced Hitchcock transportation problem
    • Brenner, U., A faster polynomial algorithm for the unbalanced Hitchcock transportation problem. Operations Research Letters 36(4) (2008), 408-413.
    • (2008) Operations Research Letters , vol.36 , Issue.4 , pp. 408-413
    • Brenner, U.1
  • 5
    • 50549085604 scopus 로고    scopus 로고
    • BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms
    • Brenner, U., Struzyna, M., and Vygen, J., BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. IEEE TCAD 27 (2008), 1607-1620.
    • (2008) IEEE TCAD , vol.27 , pp. 1607-1620
    • Brenner, U.1    Struzyna, M.2    Vygen, J.3
  • 6
    • 10044270827 scopus 로고    scopus 로고
    • Legalizing a placement with minimum total movement
    • Brenner, U., and Vygen J., Legalizing a placement with minimum total movement. IEEE TCAD 23 (2004), 1597-1613.
    • (2004) IEEE TCAD , vol.23 , pp. 1597-1613
    • Brenner, U.1    Vygen, J.2
  • 9
    • 45849140142 scopus 로고    scopus 로고
    • NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
    • Chen, T.C., Jiang, Z.W., Hsu, T.C, Chen, H.C. and Chang, Y.W., NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE TCAD 27 (7) (2008), 1228-1240.
    • (2008) IEEE TCAD , vol.27 , Issue.7 , pp. 1228-1240
    • Chen, T.C.1    Jiang, Z.W.2    Hsu, T.C.3    Chen, H.C.4    Chang, Y.W.5
  • 18
    • 2942672235 scopus 로고    scopus 로고
    • Placement Driven Synthesis Case Studies on Two Sets of Two chips: Hierarchical and Flat
    • Ossler, P.J., Placement Driven Synthesis Case Studies on Two Sets of Two chips: Hierarchical and Flat. Proc. of the ISPD(2004), 190-196.
    • Proc. of the ISPD(2004) , pp. 190-196
    • Ossler, P.J.1
  • 21
    • 47849103959 scopus 로고    scopus 로고
    • Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
    • Spindler, P., Schlichtmann, U. and Johannes F.M., Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. IEEE TCAD 27(8) (2008): 1398-1411.
    • (2008) IEEE TCAD , vol.27 , Issue.8 , pp. 1398-1411
    • Spindler, P.1    Schlichtmann, U.2    Johannes, F.M.3
  • 23
    • 79957559361 scopus 로고    scopus 로고
    • http://userweb.cs.utexas.edu/users/cart/trips/index.html
  • 24
    • 34547326796 scopus 로고    scopus 로고
    • FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
    • Viswanathan, N.,Pan, M. and Chu, C.C-N., FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. Proc. of the ASPDAC, (2007), 135-140.
    • Proc. of the ASPDAC, (2007) , pp. 135-140
    • Viswanathan, N.1    Pan, M.2    Chu, C.C.-N.3
  • 27
    • 0030718152 scopus 로고    scopus 로고
    • Algorithms for large-scale flat placement
    • Vygen, J.: Algorithms for large-scale flat placement. Proc. of the DAC (1997), 746-751.
    • Proc. of the DAC (1997) , pp. 746-751
    • Vygen, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.