Constraint driven I/O planning and placement for chip-package co-design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 207-212

  Xiong, Jinjun ^a   Wong, Yiu Chung ^b   Sarto, Egino ^b   He, Lei ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Rio Design Automation Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; CONSTRAINT THEORY; INPUT OUTPUT PROGRAMS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; PROBLEM SOLVING; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

CHIP DESIGNS; I/O CELLS; MULTI-STEP ALGORITHMS; TURN AROUND TIME;

MICROPROCESSOR CHIPS;

EID: 33748607968     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118356     Document Type: Conference Paper

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