Robust 6T Si tunneling transistor SRAM design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 740-745

  Yang, Xuebei ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-DENSITY; LOW POWER; LOW STATIC POWER; ORDERS OF MAGNITUDE; P-TYPE; PROCESS VARIATION; READ OPERATION; SRAM APPLICATIONS; SRAM CELL; SRAM DESIGN; STATIC POWER; TUNNELING FIELD-EFFECT TRANSISTORS; UNIDIRECTIONAL CONDUCTION;

CONFERENCE CALLS; GATES (TRANSISTOR); LOGIC DESIGN; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

TRANSISTORS;

EID: 79957563762     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. International Technology Roadmap for Semiconductors. http://public.itrs. net/.
2. K. Zhang et al., "SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction," IEEE Journal of Solid-State Circuits, vol. 40, pp. 895-901, 2005.
3. A. Pavlov and M. Sachdev, CMOS SRAM Circuit Design and Parametric Test in Nano-scaled Technologies. Springer, 2008.
4. C. Molina et al., "Non redundant data cache," in Int. Symp. Low Power Electronics and Design, pp. 274-277, 2003.
5. F. Hamzaoglu et al., "Dual-Vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13μm technology generation," in Intl. Symp. Low Power Electronics and Design, pp. 15-19, 2000.
6. R. W. Mann et al., "Ultralow-power SRAM technology," IBM Journal of Research and Development, vol. 47, pp. 553-566, 2003.
7. M. Sharifkhani et al., "Segmented virtual ground architecture for low-power embedded SRAM," IEEE Trans. VLSI Systems, vol. 15, pp. 196-205, 2007.
8. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI devices. Cambridge University Press, 2009.
9. W. M. Reddick et al., "Silicon surface tunnel transistor," Applied Physics Letters, vol. 67, pp. 494-496, 1995.
10. P. F. Wang et al., "Complementary tunneling transistor for low power applications," Solid-State Electronics, vol. 48, pp. 2281-2286, 2004.
11. Q. Zhang et al., "Low-subthreshold-swing tunnel transistors," IEEE Electron Device Letters, vol. 27, pp. 297-300, 2006.
12. W. Y. Choi et al., "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Letters, vol. 28, pp. 743-745, 2007.
13. S. Saurabh et al., "Estimation and compensation of process induced variations in nanoscale tunnel field effect transistors (TFETs) for improved reliability," IEEE Trans. Device and Materials Reliability, vol. 11, pp. 1-21, 2010.
14. D. Kim et al., "Low power circuit design based on heterojunction tunneling transistors (HETTs)," in Intl. Symp. Low Power Electronics and Design, pp. 219-224, 2009.
15. J. Singh et al., "A novel Si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications," in Asia and South Pacific Design Automation Conference, pp. 181-186, 2010.
16. Y. Cao et al., "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Custom Integrated Circuits Conference, pp. 201-204, 2000.
17. C. T-Chuang et al., "High-performance SRAM in nanoscale CMOS: Design challenges and techniques," in IEEE Intl. Workshop on Memory Technology, Design, and Testing, pp. 4-12, 2007.
18. W. Dehaene et al., "Embedded SRAM design in deep deep submicron technologies," in European Solid State Conference, pp. 384-391, 2007.
19. J. Wang et al., "Analyzing static and dynamic write margin for nanometer SRAMs," in Int. Symp. Low Power Electronics and Design, pp. 129-134, 2008.
20. V. Chandra et al., "On the efficacy of write-assist techniques in low voltage nanoscale SRAMs," in Proc. Design, Automation and Test in Europe, pp. 345-350, 2010.
21. R. W. Mann et al., "Impact of circuit assist methods on margin and performance in 6T SRAM," Solid-State Electronics, vol. 54, pp. 1398-1407, 2010.