Low power circuit design based on heterojunction tunneling transistors (HETTs)

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 219-224

  Kim, Daeyeon ^a   Lee, Yoonmyung ^a   Cai, Jin ^b   Lauer, Isaac ^b   Chang, Leland ^b   Koester, Steven J ^b   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Low power applications; SRAM design; Tunneling transistor

Indexed keywords

ASYMMETRIC CURRENTS; CIRCUIT BEHAVIORS; DEVICE CHARACTERISTICS; DEVICE MODELS; DYNAMIC POWER; LEAKAGE POWER; LOW POWER APPLICATION; LOW SUPPLY VOLTAGES; LOW VOLTAGE OPERATION; LOW-POWER CIRCUIT; LOW-POWER CIRCUIT DESIGN; LOWER LIMITS; MILLER CAPACITANCE; MOSFETS; OFF CURRENT; RING OSCILLATOR; SI/SIGE HETEROJUNCTION; SRAM CELL; SRAM DESIGN; SUBTHRESHOLD SWING; TECHNOLOGY COMPUTER AIDED DESIGN; VERILOG-A;

COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD EFFECT TRANSISTORS; HETEROJUNCTIONS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; LOW POWER ELECTRONICS; MOSFET DEVICES; NONVOLATILE STORAGE; OSCILLATORS (ELECTRONIC); POWER ELECTRONICS; TUNNELING (EXCAVATION); WIND TUNNELS;

STATIC RANDOM ACCESS STORAGE;

EID: 70449700259     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594287     Document Type: Conference Paper

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