Segmented virtual ground architecture for low-power embedded SRAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 2, 2007, Pages 196-205

  Sharifkhani, Mohammad ^a,b   Sachdev, Manoj ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Leakage current; Low leakage; Low power; Memories; Power consumption; Random access memories (RAM); Static access random memories (SRAM)

Indexed keywords

SEGMENTED VIRTUAL GROUNDING (SVGND); STATIC POWER CONSUMPTION;

BIT ERROR RATE; ELECTRIC GROUNDING; EMBEDDED SYSTEMS; ENERGY DISSIPATION; LEAKAGE CURRENTS; VIRTUAL REALITY;

STATIC RANDOM ACCESS STORAGE;

EID: 34047098776     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893584     Document Type: Article

References (13)

1. K. Itoh, K. Sasaki. and Y. Nakagome, 'Trends in low-power SRAM circuit technologies." Proc. IEEE. vol. 83. no. 4, pp. 524-543, Apr. 1995.
2. K. Kanda. S. Hattori, and T. Sakurai, "90% write power-saving SRAM using sense-amplifying memory cell," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 929-933, Jun. 2004.
3. N. Shibata, "A switched virtual-GND level technique for fast and low power SRAM's." IEICE Trans. Electron., vol. E80-C, pp. 1598-1607, 1997.
4. B. S. Amrutur and M. A. Horowitz, "A replica technique for wordline and sense control in low-power SRAM's," IEEE J. Solid-State Circuits, vol. 33. no. 8, pp. 1208-1219, Aug. 1998.
5. H. Mizuno and T. Nagano, "Driving source-line cell architecture for sub-l-V highspeed low-power applications," IEEE J. Solid-State Circuits, vol. 31. no. 4, pp. 552-557, Apr. 1996.
6. K. W. Mai et al., "Low-power SRAM design using half-swing pulse-mode techniques," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1659-1671, Nov. 1998.
7. B. Yang and L. Kim, "A low power SRAM using hierarchical bit-line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40. no. 6, pp. 1366-1376, Jun. 2005.
8. R. Gu and M. Elmasry, "Power dissipation analysis and optimization of deep submicron CMOS digital circuits." IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 707-713, May 1996.
9. Y. Nakagome. M. Horiguchi, T. Kawahara, and K. Itoh. "Review and prospect of low-voltage RAM circuits," IBM J. Res. Dec., vol. 47, no. 5/6, pp. 525-552, Sep. 2003.
10. H. Veendrick, "The behavior of flip-flops used as synchronizers and prediction of their failure rate," IEEE J. Solid-State Circuits, vol. SC-15, no. 2, pp. 169-176, Apr. 1980.
11. M. Matsumiya et al., "A 15-ns 16-Mb CMOS SRAM with interdigitated bit-line architecture." IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1497-1503, Nov. 1992.
12. S. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies. New York: Springer-Verlag, 2006.
13. K. Itoh, VLSI Memory Chip Design. New York: Springer-Verlag, 2001.