A novel Si-tunnel FET based SRAM design for ultra low-power 0.3V V DD applications

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 181-186

  Singh, J ^a   Ramakrishnan, K ^b   Mookerjea, S ^b   Datta, S ^b   Vijaykrishnan, N ^b   Pradhan, D ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; LEAKAGE REDUCTION; LOW LEAKAGE; LOW POWER; LOW SUPPLY VOLTAGES; LOW VOLTAGES; MOSFETS; RELIABLE OPERATION; SILICON AREA; SRAM CELL; SRAM DESIGN; STABILITY MARGINS; SUB-THRESHOLD LEAKAGE; SUBTHRESHOLD; TUNNEL FET; TUNNEL FIELD EFFECT TRANSISTOR; ULTRA-LOW-VOLTAGE; ULTRALOW POWER APPLICATION;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; LOGIC DESIGN; WIND TUNNELS;

STATIC RANDOM ACCESS STORAGE;

EID: 77951235032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419897     Document Type: Conference Paper

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