On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 345-350

  Chandra, Vikas ^a   Pietrzyk, Cezary ^a   Aitken, Robert ^a  

^a ARM R and D   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER TECHNOLOGIES; LOW VOLTAGES; LOWER VOLTAGES; MINIMUM OPERATING VOLTAGES (VMIN); PROCESS VARIATION; READ NOISE MARGINS; SUPPLY VOLTAGES; WRITE OPERATIONS;

STATIC RANDOM ACCESS STORAGE;

EID: 77953117045     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457179     Document Type: Conference Paper

References (15)

1. A. J. Bhavnagarwala et al, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE Journal of Solid-State Circuits, Vol. 36, pp. 658-665, Apr. 2001.
2. L. Chang et al, "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," IEEE Journal of Solid-State Circuits, Vol. 43, pp. 956-963, Apr. 2008.
3. W. Dehaene et al, "Embedded SRAM design in deep deep submicron technologies," European Solid-State Circuits Conference (ESSCIRC), pp. 384-391, 2007.
4. W. Dong et al, "SRAM Dynamic Stability: Theory, Variability and Analysis," Intl. Conf. on Computer Aided Design (ICCAD), pp. 378-385, 2008.
5. M. Iijima et al, "Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation," Journals of Computers, Vol. 3, No. 5, May 2008
6. M. Khellah et al, "Read and Write Circuit Assist Techniques for Improving Vccmin of Dense 6T SRAM Cell," Intl. Conf. on IC Design and Technology, June 2008.
7. K. Nii et al, "A 45-nm Bulk CMOS Embedded SRAM with Improved Immunity Against Process and Temperature Variations," IEEE Journal of Solid-State Circuits, Vol. 43, Jan 2008.
8. H. Pilo et al, "An SRAM design in 65nm technology node featuring read and write-assist circuits to expand operating voltage," IEEE Journal of Solid-State Circuits, Vol. 42, Apr 2007.
9. N. Shibata et al "A 0.5V 25 MHz 1mW 256kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment - Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme," IEEE Journal of Solid-State Circuits, Vol. 41, Mar 2006.
10. C. C. Wang et al, "A Boosted Wordline Voltage Generator for Low Voltage Memories," ICECS, 2003.
11. J. Wang et al, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs," ISLPED, 2008.
12. M. Yamaoka et al, "90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique," IEEE Journal of Solid-State Circuits, Vol. 41, Apr 2006.
13. H. S. Yang et al, "Scaling of 32nm Low Power SRAM with High-K Metal Gate," IEEE Intl. Electron Devices Meeting, 2008.
14. K. Zhang et al, "Low Power SRAMs in nanoscale CMOS technologies," IEEE Trans. Electron Devices, Vol. 55, No. 1, pp. 145-151, Jan. 2008.
15. K. Zhang et al, "A 3 GHz 70 Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply," IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, Jan 2006.