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1
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71049179902
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New approach to form EOT-scalable gate stack with strontium germanide interlayer for high-k/Ge MISFETs
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Y. Kamata, A. Takashima, Y. Kamimuta, and T. Tezuka, "New approach to form EOT-scalable gate stack with strontium germanide interlayer for high-k/Ge MISFETs," VLSI Technology, pp.78-79, 2009.
-
(2009)
VLSI Technology
, pp. 78-79
-
-
Kamata, Y.1
Takashima, A.2
Kamimuta, Y.3
Tezuka, T.4
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2
-
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71049134867
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Physical origins of mobility enhancement of Ge pMISFETs with Si passivation layers
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N. Taoka, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and S. Takagi, "Physical origins of mobility enhancement of Ge pMISFETs with Si passivation layers," VLSI Technology, pp.80-81, 2009.
-
(2009)
VLSI Technology
, pp. 80-81
-
-
Taoka, N.1
Mizubayashi, W.2
Morita, Y.3
Migita, S.4
Ota, H.5
Takagi, S.6
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3
-
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71049164730
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Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI
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J.Mitard, C. Shea, B. DeJaeger, A. Pristera, G.Wang, M. Houssa, G. Eneman, G. Hellings, W.-E. Wang, J.C. Lin, F.E. Leys, R. Loo, G. Winderickx, E. Vrancken, A. Stesmans, K. DeMeyer, M. Caymax, L. Pantisano, M. Meuris, and M. Heyns, "Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI," VLSI Technology, pp.82-83, 2009.
-
(2009)
VLSI Technology
, pp. 82-83
-
-
Mitard, J.1
Shea, C.2
DeJaeger, B.3
Pristera, A.4
Wang, G.5
Houssa, M.6
Eneman, G.7
Hellings, G.8
Wang, W.-E.9
Lin, J.C.10
Leys, F.E.11
Loo, R.12
Winderickx, G.13
Vrancken, E.14
Stesmans, A.15
DeMeyer, K.16
Caymax, M.17
Pantisano, L.18
Meuris, M.19
Heyns, M.20
more..
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4
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77950143676
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Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si cap and high-k metal gate stacks
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April
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J. Oh, P. Majhi, R. Jammy, R. Joe, A. Dip, T. Sugawara, Y. Akasaka, T. Kaitsuka, T. Arikado, and M. Tomoyasu, "Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si cap and high-k metal gate stacks," International Symposium on VLSI-TSA, April 2009.
-
(2009)
International Symposium on VLSI-TSA
-
-
Oh, J.1
Majhi, P.2
Jammy, R.3
Joe, R.4
Dip, A.5
Sugawara, T.6
Akasaka, Y.7
Kaitsuka, T.8
Arikado, T.9
Tomoyasu, M.10
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6
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33646072123
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Hybrid-orientation technology (HOT): Opportunities and challenges
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M. Yang, V.W.C. Chan, K.K. Chan, L. Shi, D.M. Fried, J.H. Stathis, A.I. Chou, E. Gusev, J.A. Ott, L.E. Burns, M.V. Fischetti, and M. Ieong "Hybrid-orientation technology (HOT): Opportunities and challenges," IEEE Trans. Electron Devices, vol.53, p.965, 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, pp. 965
-
-
Yang, M.1
Chan, V.W.C.2
Chan, K.K.3
Shi, L.4
Fried, D.M.5
Stathis, J.H.6
Chou, A.I.7
Gusev, E.8
Ott, J.A.9
Burns, L.E.10
Fischetti, M.V.11
Ieong, M.12
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8
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77952387234
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Experimental demonstration of high mobility Ge NMOS
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D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P.A. Pianetta, H.S.-P. Wong, and K. Saraswat, "Experimental demonstration of high mobility Ge NMOS," IEDM Tech. Dig., p.455, 2009.
-
(2009)
IEDM Tech. Dig.
, pp. 455
-
-
Kuzum, D.1
Krishnamohan, T.2
Nainani, A.3
Sun, Y.4
Pianetta, P.A.5
Wong, H.S.-P.6
Saraswat, K.7
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9
-
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77952333907
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Record-high electron mobility in Ge n-MOSFETs exceeding Si universality
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C.H. Lee, T. Nishimura, N. Saido, K. Nagashio, K. Kita, and A. Toriumi, "Record-high electron mobility in Ge n-MOSFETs exceeding Si universality," IEDM Tech. Dig., p.457, 2009.
-
(2009)
IEDM Tech. Dig.
, pp. 457
-
-
Lee, C.H.1
Nishimura, T.2
Saido, N.3
Nagashio, K.4
Kita, K.5
Toriumi, A.6
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10
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62549137369
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Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe
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March
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J. Huang, P.D. Kirsch, J. Oh, S.H. Lee, P. Majhi, H.R. Harris, D.C. Gilmer, G. Bersuker, D. Heh, C.S. Park, C. Park, H.-H. Tseng, and R. Jammy, "Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe," IEEE Electron Device Lett., vol.30, no.3, pp.285-287, March 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.3
, pp. 285-287
-
-
Huang, J.1
Kirsch, P.D.2
Oh, J.3
Lee, S.H.4
Majhi, P.5
Harris, H.R.6
Gilmer, D.C.7
Bersuker, G.8
Heh, D.9
Park, C.S.10
Park, C.11
Tseng, H.-H.12
Jammy, R.13
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11
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77957875412
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SiGe CMOS on (110) channel orientation with mobility boosters: Surface orientation, channel directions, and uniaxial strain
-
June
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J. Oh, S.-H. Lee, K.-S. Min, J. Huang, B.G. Min, B. Sassman, K. Jeon, W.-Y. Loh, J. Barnett, I. Ok, C.-Y. Kang, C. Smith, D.-H. Ko, P.D. Kirsch, and R. Jammy, "SiGe CMOS on (110) channel orientation with mobility boosters: Surface orientation, channel directions, and uniaxial strain," VLSI Technology, pp.39-40, June 2010.
-
(2010)
VLSI Technology
, pp. 39-40
-
-
Oh, J.1
Lee, S.-H.2
Min, K.-S.3
Huang, J.4
Min, B.G.5
Sassman, B.6
Jeon, K.7
Loh, W.-Y.8
Barnett, J.9
Ok, I.10
Kang, C.-Y.11
Smith, C.12
Ko, D.-H.13
Kirsch, P.D.14
Jammy, R.15
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12
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11144354892
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A logic nanotechnology featuring strained-silicon
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S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K.Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol.25, pp.191-193, 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Ma, Z.9
Mcintyre, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
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13
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71049190976
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Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective masses
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J. Oh, I. Ok, C.-Y. Kang, M. Jamil, S.-H. Lee, W.-Y. Loh, J. Huang, B. Sassman, L. Smith, S. Parthasarathy, B.E. Coss, W.-H. Choi, H.-D. Lee, M. Cho, S.K. Banerjee, P. Majhi, P.D. Kirsch, H.-H. Tseng, and R. Jammy, "Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective masses," VLSI Technology, pp.238-239, 2009.
-
(2009)
VLSI Technology
, pp. 238-239
-
-
Oh, J.1
Ok, I.2
Kang, C.-Y.3
Jamil, M.4
Lee, S.-H.5
Loh, W.-Y.6
Huang, J.7
Sassman, B.8
Smith, L.9
Parthasarathy, S.10
Coss, B.E.11
Choi, W.-H.12
Lee, H.-D.13
Cho, M.14
Banerjee, S.K.15
Majhi, P.16
Kirsch, P.D.17
Tseng, H.-H.18
Jammy, R.19
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