CCSimP — An instruction-level costum-configurable processor for FPLDs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1142, Issue , 1996, Pages 280-289

  Salcic, Zoran ^a   Maundr, Bruce ^a  

^a UNIVERSITY OF AUCKLAND   (New Zealand)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; PROGRAM COMPILERS;

APPLICATION SPECIFIC; CONFIGURABLE PROCESSORS; CUSTOM COMPUTING MACHINES; DESIGN METHODOLOGY; EMBEDDED APPLICATION; HARDWARE AND SOFTWARE; INSTRUCTION-LEVEL; QUALITY OF DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 21444444958     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61730-2_30     Document Type: Conference Paper

References (8)

1. [DANE 95] Danecek J., Drapal F., Pluhacek A., Salcic Z., Servit M. A Simple Processor for Custom Computing Machines, Journal of Microcomputing Applications, Academic Press, 1995
2. [GALT 92] Gal T., Agusa K., Ohno Y. Educational Purpose Microprocessor Implemented with User-Programmable Gate Arrays, Field Programmable Logic and Applications, Vienna 1992
3. [GRUE 92] Gruenbacher H., Jaud A. JAPROC - A 8-bit Micro Controller Design and its Test Environment, Field Programmable Logic and Applications, Vienna 1992
4. [SALC 96] Salcic Z SimP - A Simple Custom-Configurable Processor Implemented in FPGA, Auckland University Dept, of EEE Internal Report, 1996
5. [SALC 96a] Salcic Z, Maunder B SimP - a Core for FPLD-based Custom-Configurable Processors, Accepted for lntn'1 1996 ASIC Conference-ASICON, Shanghai 1996
6. [WIRT 94] Wirthlin M J, Hutchings B L, Gilson K L The Nano Processor: a Low Resource Reconfigurable Processor, IEEE Workshop on FPGAs for Custom Computing Machines, 1994, IEEE Computer Soc. Press, 1994
7. [WIRT 95] Wirthlin M J, Hutchings A Dynamic Instruction Set Computer, IEEE Symposium on FPGAs for Custom Computing Machines, 1995
8. [WOLL 93] Wollan V. A Design Methodology Achieving Fast Development Cycles for Complex VLSI Architectures, EURO ASIC Conference, Paris 1993