A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 79-80

  Salihundam, Praveen ^a   Jain, Shailendra ^a   Jacob, Tiju ^a   Kumar, Shasi ^a   Erraguntla, Vasantha ^a   Hoskote, Yatin ^b   Vangal, Sriram ^b   Ruhl, Gregory ^b   Kundu, Partha ^b   Borkar, Nitin ^b  

^a Microprocessor Research   (India)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALLOCATORS; BISECTION BANDWIDTH; MESH NETWORK; NET WORK UTILIZATION; PACKET-SWITCHED; PENTIUM; ROUTE PRE-COMPUTATION; VIRTUAL CHANNELS;

ENERGY EFFICIENCY; ROUTERS;

VLSI CIRCUITS;

EID: 77957974226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560277     Document Type: Conference Paper

References (6)

1. J. Howard et al., "A 48-Core IA-32 Message Passing Processor with DVFS in 45nm CMOS", ISSCC, 2010, in press.
2. Y. Tamir et al., IEEE trans. on computers, pp. 725-737, June. 1992.
3. Dongkook et al., IEEE Symposium on High-Performance Interconnects, pp. 15-20, 2002.
4. Mullins et al, ASP DAC, pp. 164-169, 2006.
5. M. Heath et al, IEEE Trans. on Computers, pp.1532-1546, Dec 2005.
6. W.J Dally, "Virtual-channel flow control" IEEE Transactions on Parallel and Distributed Systems, pp.194-205, Mar 1992.