Controlling NBTI degradation during static burn-in testing

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 597-602

  Chakraborty, Ashutosh ^a   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; BURN-IN; BURN-IN TEST; BURN-IN TESTING; CRITICAL PATH DELAYS; INPUT PINS; LEAKAGE REDUCTION; NANOMETER VLSI; NEGATIVE BIAS TEMPERATURE INSTABILITY; OPERATING TEMPERATURE; PMOS DEVICES; SUPPLY VOLTAGES; VLSI CHIP;

COMPUTER AIDED DESIGN; DELAY CIRCUITS; INTEGRATED CIRCUIT TESTING; THERMODYNAMIC STABILITY;

DEGRADATION;

EID: 79952909642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722259     Document Type: Conference Paper

References (22)

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