Skew management of NBTI impacted gated clock trees

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2010, Pages 127-133

  Chakraborty, Ashutosh ^a   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Clock gating; Clock skew; NBTI

Indexed keywords

CLOCK BUFFER; CLOCK GATING; CLOCK SIGNAL PATHS; CLOCK SKEWS; CLOCK TREE; DELAY EQUATIONS; FAILURE MECHANISM; GATED CLOCKS; IC DESIGNS; INTEGER LINEAR PROGRAMS; INTEGRATED CLOCK GATING; MINIMIZATION PROBLEMS; NEGATIVE BIAS TEMPERATURE INSTABILITY; NOR GATES; OUTPUT STAGES; SIGNAL PROBABILITY;

ADAPTIVE SYSTEMS; ELECTRIC CLOCKS; INTEGER PROGRAMMING; OPTIMIZATION; TELECOMMUNICATION NETWORKS;

MACHINE DESIGN;

EID: 77952275034     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1735023.1735056     Document Type: Conference Paper

References (13)

1. S. Bhardwaj et al., "Predictive modeling of the nbti effect for reliable design," IEEE Custom Integrated Circuits, pp. 189-192, Sept. 2006.
2. W. Wang et al., "The impact of nbti on the performance of combinational and sequential circuits," DAC '07. 44th ACM/IEEE, pp. 364-369, June 2007.
3. S. Kumar et al., "Impact of nbti on sram read stability and design for reliability," ISQED '06., pp. 6 pp.-,March 2006.
4. M. A. Alam et al., "A comprehensive model of pmos nbti degradation," Microelectronic Reliability, pp. 71-81, Sept. 2005.
5. S. Kumar et al., "Nbti-aware synthesis of digital circuits," in DAC. 44th ACM/IEEE, pp. 370-375, June 2007.
6. G. Chen et al., "Dynamic nbti of pmos transistors and its impact on device lifetime," in Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International, pp. 196-202, March-4 April 2003.
7. S. V. Kumar et al., "An analytical model for negative bias temperature instability," in ICCAD '06, (New York, NY, USA), pp. 493-496, ACM, 2006.
8. R. Vattikonda et al., "Modeling and minimization of pmos nbti effect for robust nanometer design," in DAC, (New York, NY, USA), pp. 1047-1052, ACM, 2006.
9. S. Mahapatra et al., "On the generation and recovery of interface traps in mosfets subjected to nbti, fn, and hci stress," Electron Devices, IEEE Transactions on, vol. 53, pp. 1583-1592, July 2006.
10. R. Vattikonda et al., "A new simulation method for nbti analysis in spice environment," ISQED, pp. 41-46, March 2007.
11. J. M. Cohn, "Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design," November 2003.
12. A. Chakraborty et al., "Analysis and optimization of nbti induced clock skew in gated clock trees," DATE, pp. 849-855, March 2009.
13. "Corporate website." http://www.nangate.com.