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Volumn , Issue , 2009, Pages 296-299

Analysis and optimization of NBTI induced clock skew in gated clock trees

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; ELECTRIC CLOCKS; FAILURE (MECHANICAL); FORESTRY; THERMODYNAMIC STABILITY; TREES (MATHEMATICS);

EID: 70350053279     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090675     Document Type: Conference Paper
Times cited : (22)

References (13)
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  • 2
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  • 3
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    • A scalable algorithm for rtl insertion of gated clocks based on odcs computation
    • Jan
    • P. Babighian et al., "A scalable algorithm for rtl insertion of gated clocks based on odcs computation," TCAD, vol. 24, pp. 29-42, Jan. 2005.
    • (2005) TCAD , vol.24 , pp. 29-42
    • Babighian, P.1
  • 4
    • 33745686653 scopus 로고    scopus 로고
    • On the generation and recovery of interface traps in mosfets subjected to nbti, fn, and hci stress
    • July
    • S. Mahapatra et al., "On the generation and recovery of interface traps in mosfets subjected to nbti, fn, and hci stress," Electron Devices, IEEE Transactions on, vol. 53, pp. 1583-1592, July 2006.
    • (2006) Electron Devices, IEEE Transactions on , vol.53 , pp. 1583-1592
    • Mahapatra, S.1
  • 5
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    • New York, NY, USA, pp, ACM
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    • (2006) DAC 2006 , pp. 1047-1052
    • Vattikonda, R.1
  • 6
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    • An analytical model for negative bias temperature instability
    • New York, NY, USA, pp, ACM
    • S. V. Kumar et al., "An analytical model for negative bias temperature instability," in ICCAD 2006, (New York, NY, USA), pp. 493-496, ACM, 2006.
    • (2006) ICCAD 2006 , pp. 493-496
    • Kumar, S.V.1
  • 7
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    • A new simulation method for nbti analysis in spice environment
    • March
    • R. Vattikonda et al., "A new simulation method for nbti analysis in spice environment," ISQED 2007, pp. 41-46, March 2007.
    • (2007) ISQED 2007 , pp. 41-46
    • Vattikonda, R.1
  • 8
    • 70350057390 scopus 로고    scopus 로고
    • Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
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  • 9
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  • 10
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.