Exact and heuristic approaches to input vector control for leakage power reduction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 527-532

  Gao, Feng ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INPUT VECTORS; LEAKAGE POWER REDUCTION; MIXED-INTEGER LINEAR PROGRAMMING (MLP); VECTOR CONTROL;

BOOLEAN ALGEBRA; CONTROL SYSTEM ANALYSIS; FUNCTIONS; HEURISTIC METHODS; LINEAR PROGRAMMING; MATHEMATICAL MODELS; VECTORS;

LEAKAGE CURRENTS;

EID: 16244401103     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382634     Document Type: Conference Paper

References (14)

1. A. Abdollahi et al., "Runtime mechanisms for leakage current reduction in CMOS VLSI Circuits", Proc. ISLPED, 2002, pp.213-218.
2. E. Boros & P.L. Hammer, "Pseudo-Boolean optimization", Rutgers University, Rutcor Research Report, 2001.
3. A. Gupta & J.P. Hayes, "CLIP: Integer-programming-based optimal layout synthesis of 2D CMOS cells", ACM TODAES, July 2000, pp.510-547.
4. G.D. Hachtel & F.Somenzi. Logic Synthesis and Optimization, Boston: Kluwer, 2000.
5. J. Halter & F. Najm, "A gate-level leakage power reduction method for ultra low power CMOS circuits", Proc. CICC, 1997, pp 475-478.
6. ILOG cplex webpage. http://www.ilog.com/products/cplex/.
7. Semiconductor Industry Association, 2003 Int'l Technology Roadmap for Semiconductors, http://public.itrs.net/.
8. M.C. Johnson et al., "Leakage control with efficient use of transistor stacks in single threshold CMOS", Proc. DAC, 1999, pp. 442-445.
9. T. Kuroda et al., "A 0.9-V, 150-MHz, 10-mW, 4 mm2 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme", IEEE JSSC, Nov. 1996, pp.1770-1779.
10. S. Naidu & E. Jacobs, "Minimizing stand-by leakage power in static CMOS circuits", Proc. DATE, 2001, pp.370-376.
11. R.M. Rao et al., "A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits", Proc. ICCAD, 2003, pp 689-692.
12. S. Shigematsu et al., "A 1-V high-speed MTCMOS circuit scheme for power-down applications", Digest Symp. VLSI Circuits, 1995, pp. 125-126.
13. Y-F. Tsai et al., "Implications of technology scaling on leakage reduction techniques", Proc. DAC, 2003, pp. 187-190.
14. Y. Ye et al., "A new technique for standby leakage reduction in high-performance circuits", Proc. Symp. VLSI Circuits, 1998, pp.40-41.