Shedding physical synthesis area bloat

VLSI Design

Volumn 2011, Issue , 2011, Pages

  Zhou, Ying ^a   Alpert, Charles J ^a   Li, Zhuo ^a   Sze, Cliff ^a   Trevillyan, Louise H ^b  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA CONTROL; AREA REDUCTION; BUFFER INSERTION; CONGESTION PROBLEM; DESIGN FLOWS; DIE AREA; GATE SIZING; GROWTH REDUCTION; INDUSTRIAL DESIGN; LOW-POWER CONSUMPTION; OPTIMIZED ALGORITHMS; PHYSICAL SYNTHESIS; POWER DISSIPATION; TIMING-DRIVEN; WIRE LENGTH;

GATES (TRANSISTOR); TRAFFIC CONGESTION;

DESIGN;

EID: 79952138060     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/2011/503025     Document Type: Review

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