Fast interconnect synthesis with layer assignment

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2008, Pages 71-77

  Li, Zhuo ^a   Alpert, Charles J ^a   Hu, Shiyan ^b   Muhmud, Tuhin ^c   Quay, Stephen T ^c   Villarrubia, Paul G ^c  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b MICHIGAN TECHNOLOGICAL UNIVERSITY   (United States)

^c IBM   (United States)

Author keywords

Buffer insertion; Interconnect synthesis; Layer assignment; Wire sizing

Indexed keywords

BUFFER INSERTION; INTERCONNECT SYNTHESIS; LAYER ASSIGNMENT; WIRE SIZING;

ELECTRIC FIELD EFFECTS; ELECTRIC POWER SYSTEM INTERCONNECTION; INSERTION LOSSES; PROBLEM SOLVING;

BUFFER CIRCUITS;

EID: 43349104586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1353629.1353648     Document Type: Conference Paper

References (18)