Fast algorithms for slew-constrained minimum cost buffering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 11, 2007, Pages 2009-2022

  Hu, Shiyan ^a   Alpert, Charles J ^b   Hu, Jiang ^a   Karandikar, Shrirang K ^b   Li, Zhuo ^b   Shi, Weiping ^a   Sze, C N ^b  

^a Texas AandM University   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Buffer insertion; Input slew; Interconnect; NP complete; Slew constraint

Indexed keywords

BUFFER INSERTION; INPUT SLEW; INTERCONNECT; NP-COMPLETE; SLEW CONSTRAINT;

BUFFER CIRCUITS; MARINE BIOLOGY; SYSTEMS ENGINEERING;

ALGORITHMS;

EID: 43349103479     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.906477     Document Type: Article

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