Reliability assessment of the 20 um pitch micro-joints within a 3DIC assembly under various environments

International Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings

Volumn , Issue , 2010, Pages

  Huang, Shin Yi ^a   Chang, Tao Chih ^a   Cheng, Ren Shin ^a   Chang, Jing Yao ^a   Leu, Fang Jun ^a   Lu, Yu Lan ^a   Yang, Tsung Fu ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH TEMPERATURE STORAGE TEST; HIGH-DENSITY INTERCONNECTION; JEDEC STANDARDS; MICRO-BUMPS; MICROGAPS; ON-WAFER; PACKAGING TECHNOLOGIES; PB-FREE; PB-FREE SOLDER BUMP; PEAK TEMPERATURES; PRESSURE COOKER TESTS; RELIABILITY ASSESSMENTS; RELIABILITY PERFORMANCE; RELIABILITY TEST; SCANNING ACOUSTIC MICROSCOPES; STORAGE TESTS; TEMPERATURE CYCLING TESTS; TEST CONDITION; TEST VEHICLE; THERMAL SHOCK TESTS; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA; UNDER BUMP METALLIZATION; UNDERFILLS;

ACOUSTIC MICROSCOPES; CHIP SCALE PACKAGES; ELECTRONIC EQUIPMENT MANUFACTURE; INTEGRATED CIRCUITS; LEAD; MICROSYSTEMS; PASSIVATION; RELIABILITY ANALYSIS; SILICON; SILICON WAFERS; SOLDERING; SOLDERING ALLOYS; THREE DIMENSIONAL;

TESTING;

EID: 79951635391     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2010.5699594     Document Type: Conference Paper

References (14)

1. J. U. Knickerbocker, et al., "Three-dimensional silicon integration," IBM Journal of Research and Development, Vol. 52, No. 6, pp. 553-569, 2008.
2. P. G. Emma. et al., "Is 3D chip technology the next growth engine for performance improvement?," IBM Journal of Research and Development, Vol. 52, No. 6, pp. 541-552.
3. E. Beyne, "3D Interconnection and packaging: impending reality or still a dream?" ISSCC, 15-19 February 2004; San Francisco, CA, pp. 138-145.
4. P. Ramm et al., "Through Silicon Via Technology - Process and Reliability for Wafer-Level 3D System Integration," Electronic Components and Technology Conference (ECTC), May 27-30, 2008.
5. K. Sakuma et al., "3D chip-stacking technology with throughsilicon vias and low volume lead-free interconnections," IBM J. Res. & Dev. 52. No. 6, pp. 611-622, 2008.
6. J.-Q. Lu et al., "Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs," IITC, 2003, pp. 74-76.
7. Fukushima T., et al., "New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique, " IEDM 2007. IEEE International, Dec. 2007, pp. 985-988.
8. Sakuma, K. et al, "Characterization of Stacked Die using Die-to- Wafer Integration for High Yield and Throughput," Proc 58th Electronic Components and Technology Conf, Orlando, FL, May. 2008, pp. 18-23.
9. Kurita. Y. et al, "A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology," Proc 57th Electronic Components and Technology Conf, Reno, NV, June. 2007, pp. 821-829.
10. Hwang Jihwan et al., "Fine pitch chip interconnection technology for 3D integration ," Electronic Components and Technology Conference (ECTC), 2010 , pp. 1399-1403.
11. S. L. Wright, et al., "Characterization of Micro-bump C4 interconnects for Si-Carrier SOP applications," 55th Electronic Components and Technology Conference, 2006, pp. 633-640.
12. H. Gan, S. L. et al., "Ph-free micro joints (50 m pitch) for the ́ next generation micro-systems: the fabrication, assembly and characterization," 56th Electronic Components and Technology Conference, 2006, pp. 1210-1215.
13. Aibin. Yu, et al., "Study of 15 um pitch solder microbumps for 3DIC integration," Electronic Components and Technology Conference, pp. 6-10, 2009.
14. Zhuqing Zhang and C.P. Wong, "Recent advances in flip-chip underfill: materials, process, and reliability," IEEE Transactions on Advanced Packaging, pp. 515-524, 2004.