Fine pitch chip interconnection technology for 3D integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1399-1403

  Hwang, Jihwan ^a   Kim, Jongyeon ^a   Kwon, Woonseong ^a   Kang, Unbyoung ^a   Cho, Taeje ^a   Kang, Sayoon ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BONDABILITY; BONDING CONDITIONS; BONDING TECHNIQUES; CHIP INTEGRATION; CHIP STACKING; CHIP-ON-CHIP; ELECTRICAL CONNECTION; ELECTRICAL PERFORMANCE; FINE PITCH; FLIP CHIP BONDING; FLUXLESS; HIGHER YIELD; IC PACKAGING; INTERCONNECTION TECHNOLOGY; LOW-POWER CONSUMPTION; MICRO-JOINING; ON-WAFER; PIN COUNTS; SI CHIPS; SMALL FORM FACTORS; THERMO-COMPRESSION; THROUGH-SILICON-VIA; WARPAGES;

APPROXIMATION THEORY; CHIP SCALE PACKAGES; ELECTRIC CONNECTORS; JOINING; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 77955190632     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490821     Document Type: Conference Paper

References (8)

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7. Kim, J. Y. et al, "Effect of Cu Content on the Mechanical Reliability of Ni/Sn-3.5Ag Sysetem," J. Mater. Res., Vol.22, No.3, 2007, pp. 770-776.
8. Wakiyama, S. et al, "Novel Low-Temperature CoC Interconnection Technology for Multichip LSI (MCL)." Proc 57th Electronic Components and Technology Conf, Reno, NV, June. 2007, pp. 610-615.