A low power and high performance SOI SRAM circuit design with improved cell stability

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2006, Pages 4-7

  Joshi, R V ^a   Chan, Y ^b   Plass, D ^b   Charest, T ^b   Freese, R ^b   Sautter, R ^b   Huott, W ^b   Srinivasan, U ^b   Rodko, D ^b   Patel, P ^b   Shephard, P ^b   Werner, T ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; SILICON ON INSULATOR TECHNOLOGY;

CELL LAYOUT; CELL STABILITY; WORDLINE DRIVERS;

STATIC RANDOM ACCESS STORAGE;

EID: 43749103785     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2006.284405     Document Type: Conference Paper

References (6)

1. R. Joshi et. al, ESSCIRC Proc., Sept 2004, pp. 411-415.
2. K. Zhang et al, ISSCC Dig. Tech. Papers, Feb 2005, pp. 474-475.
3. J. Chang, et al, ISSCC Dig. Tech. Papers, Feb 2004, pp. 496-497.
4. K. Takeda et al, ISSCC Dig. Tech. Papers, Feb 2005, pp. 478-479.
5. Y. Nakagome et al, IBM Journal of R&D, Vol 47, No. 5/6, 2003, pp. 525-552.
6. J. Tschanz et al, JSSCC, Vol 38, Nov 2003, pp. 1838-1845.