A 5.6GHz 64kB dual-read data cache for the POWER6™ processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Davis, J ^a   Plass, D ^a   Bunce, P ^a   Chan, Y ^a   Pelella, A ^a   Joshi, R ^a   Chen, A ^a   Huott, W ^a   Knips, T ^a   Patel, P ^a   Lo, K ^a   Fluhr, E ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL STABILITY; DATA CACHE; DUAL POWER SUPPLIES;

CACHE MEMORY; POLYSILICON; STATIC RANDOM ACCESS STORAGE;

PROGRAM PROCESSORS;

EID: 33947623051     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)