Spintronic logic gates for spintronic data using magnetic tunnel junctions

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 125-131

  Patil, Shruti ^a   Lyle, Andrew ^a   Harms, Jonathan ^a   Lilja, David J ^a   Wang, Jian Ping ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS DEVICES; DESIGN CIRCUITS; ELECTRONIC CIRCUITRY; ELECTRONIC DEVICE; ENERGY-DELAY; LOGIC FUNCTIONALITY; LOGIC FUNCTIONS; LOGIC OPERATIONS; LOGIC UNIT; MAGNETIC TUNNEL JUNCTION; MEMORY DEVICE; MEMORY MODULES; MEMORY UNITS; NONVOLATILE MEMORY DEVICES; POWER CONSUMPTION; SPINTRONIC CIRCUITS; SPINTRONIC DEVICE; SPINTRONICS;

COMPUTATION THEORY; DESIGN; ELECTRON DEVICES; MAGNETIC DEVICES; SEMICONDUCTOR JUNCTIONS; SWITCHING CIRCUITS; TUNNEL JUNCTIONS;

LOGIC CIRCUITS;

EID: 78650734597     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647611     Document Type: Conference Paper

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