Compiler-directed application mapping for NoC based chip multiprocessors

ACM SIGPLAN Notices

Volumn 42, Issue 7, 2007, Pages 155-157

  Chen, Guangyu ^a   Li, Feihui ^a   Kandemir, Mahmut ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Application mapping; Compilers; Network on chip (NoC); Power optimization

Indexed keywords

ENERGY UTILIZATION; MAPPING; MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS; SERVERS;

APPLICATION MAPPING; CHIP MULTIPROCESSOR; LOCALITY AWARE; NETWORK-ON-CHIP(NOC); PACKET ROUTING; PERFORMANCE-ORIENTED; POWER OPTIMIZATION; TASK-SCHEDULING;

NETWORK-ON-CHIP;

EID: 67650305372     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1273444.1254796     Document Type: Article

References (6)

1. J. M. Anderson. Automatic Computation and Data Decomposition for Multiprocessors. Ph.D. Thesis, Computer Science Department, Stanford University, March 1997.
2. L. Benini and G. D. Micheli. Powering NoCs: energy-efficient and reliable interconnect design for SoCs. In Proc. ISSS, 2001.
3. G. Chen, F. Li, and M. Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. POPL, Charleston, SC, Jan. 2006.
4. W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, Las Vegas, NV June 2001.
5. Virtutech Simics: http://www.virtutech.com/
6. H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A powerperformance simulator for interconnection networks. In Proc. MICRO, Nov. 2002.