Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 527-530

  Hecht, Ronald ^a   Kubisch, Stephan ^a   Herrholtz, Andreas ^a   Timmermann, Dirk ^a  

^a UNIVERSITY OF ROSTOCK   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; COST EFFECTIVENESS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; ROUTERS;

NETWORKS-ON-CHIP (NOC); RECONFIGURABLE RESOURCES; ROUTING RESOURCE; SYSTEMC MODEL;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746933468     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515777     Document Type: Conference Paper

References (7)

1. T. Marescaux et al, "Networks on chip as hardware components of an os for reconfigurable systems." in FPL 2003, Lisbon, Portugal, 2003, pp. 595-605.
2. R. Hecht, D. Timmermann, S. Kubisch, and E. Zeeb, "Network-on-chip basierende laufzeitsysteme für dynamische rekonfigurierbare hardware. " in ARCS Workshops, Augsburg, Germany, 2004, pp. 185-194.
3. T. Marescaux et al, "Interconnection networks enable fine-grain dynamic multi-tasking on fpgas." in FPL 2002, Montpellier, France, 2002, pp. 795-805.
4. M. Hübner et al, "Scalable application-dependent network on chip adaptivity for dynamical reconfigurable real-time systems." in FPL 2004, Leuven, Belgium, 2004, pp. 1037-1041.
5. W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks." in DAC 2001, Las Vegas, NV, USA, 2001, pp. 684-689.
6. G. J. Brebner, P. James-Roxby, E. Keller, and C. Kulkarni, "Hyper-programmable architectures for adaptable networked systems." in ASAP 2004, 2004, pp. 328-338.
7. A. Schallenberg, F. Oppenheimer, and W. Nebel, "Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS." in FDL 04, Lille, France, 2004.