Energy minimization of system pipelines using multiple voltages

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages

  Qu, Gang ^a   Kirovski, Darko ^a   Potkonjak, Miodrag ^a   Srivastava, Mani B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

COMMUNICATION PIPELINE LATENCY; PACKET FRAGMENTATION; SYSTEM PIPELINE DESIGN; TIMING CONSTRAINTS; TRANSMISSION LATENCY; VARIABLE VOLTAGE CORE BASED SYSTEM DESIGN;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0032645638     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (27)