Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 894-897

  Olson, Brian D ^a   Amusan, Oluwole A ^a   Dasgupta, Sandeepan ^a   Massengill, Lloyd W ^a   Witulski, Arthur F ^a   Bhuva, Bharat L ^a   Alles, Michael L ^a   Warren, Kevin M ^a   Ball, Dennis R ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

Guard contacts; Parasitic bipolar conduction; Singe event effects; Technology computer aided design (TCAD) modeling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION;

GUARD CONTACTS; MITIGATION; WELL CONTACT;

BIPOLAR TRANSISTORS;

EID: 34548061160     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.895243     Document Type: Conference Paper

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