Chip-level reliability study of barrier engineered (BE) floating gate (FG) flash memory devices

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 627-633

  Lue, Hang Ting ^a   Pan, Ji Fong ^b   Chang, C S ^b   Wang, Szu Yu ^c   Chang, Y F ^b   Lee, Y C ^b   Liaw, M H ^b   Chen, Y J ^c   Chen, K F ^c   Lo, Chester ^c   Huang, I J ^c   Han, T T ^c   Chen, M S ^c   Lu, W P ^c   Yang, T ^c   Chen, K C ^c   Hsieh, Kuang Yeu ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b Product Engineering Center   (Taiwan)

^c Technology Development Center   (Taiwan)

Author keywords

Barrier engineer (BE); Charge trapping memory; Component; Floating gate; Modeling; Reliability; Tunneling

Indexed keywords

BARRIER ENGINEER (BE); CHARGE TRAPPING MEMORIES; COMPONENT; FLOATING GATES; MODELING; TUNNELING;

ENGINEERS; FLASH MEMORY; NITRIDES;

RELIABILITY;

EID: 77957896717     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488758     Document Type: Conference Paper

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