Data retention, endurance and acceleration factors of NROM devices

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 502-505

  Janai, Meir ^a  

^a Saifun Semiconductors Ltd   (Israel)

Author keywords

Acceleration factor; Endurance; NROM; NVM; Product reliability; Qualification; Retention; Trapped charge

Indexed keywords

DIGITAL STORAGE; DURABILITY; RELIABILITY; SOLDERED JOINTS;

ACCELERATION FACTORS; NROM; NVM; PRODUCT RELIABILITY; QUALIFICATION; RETENTION; TRAPPED CHARGE;

ROM;

EID: 84955259397     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197799     Document Type: Conference Paper

References (7)

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2. P. Clarke, "AMD, Fujitsu, Saifun to team up on multi-bit flash," in EE Times, July 30, 2002
3. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", in IEEE Electron Device Lett., vol. 21 pp. 543-545, Nov. 2000
4. P. Pavan, R. Bez, P. Olivio, E. Zanoni, "Flesh Memory Cells an Overview, in Proc. Of the IEEE, Vol.85, No.8 pp. 1248-1271, 1997
5. E. Lusky, Y. Shacham-Diamand, I. Bloom and B. Eitan, "Electron Retention Model for Localized Charge in Oxide Nitride-Oxide (ONO) Dielectric", in IEEE Electron Device Lett., vol. 23, pp 556-558 Sep. 2002.
6. JEDEC STANDARD JESD22-A103-B "High Temperature Storage Life", JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, Aug. 2001
7. JEDEC STANDARD JESD22-A117, "Electrically Erasable Programmable ROM Program/Erase Endurance and Data Retention Test", JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, Jan. 2000