Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 10, 2010, Pages 1461-1470

  Karakonstantis, Georgios ^a   Banerjee, Nilanjan ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Low power design; power quality tradeoffs; process variation tolerance; voltage over scaling

Indexed keywords

DELAY ERRORS; GRACEFUL DEGRADATION; GRADUAL DEGRADATION; IN-PROCESS PARAMETERS; LONG-PATH; LOW-POWER COMPUTING; LOW-POWER DESIGN; LOW-POWER DISSIPATION; NOMINAL VOLTAGE; OUTPUT QUALITY; POWER SAVINGS; POWER-QUALITY TRADEOFFS; PROCESS PARAMETER VARIATIONS; PROCESS TECHNOLOGIES; PROCESS VARIATION; PROPOSED ARCHITECTURES; SUPPLY VOLTAGES; SUPPLY-VOLTAGE SCALING; VOLTAGE OVER-SCALING; VOLTAGE-SCALING;

COSINE TRANSFORMS; DEGRADATION; DISCRETE COSINE TRANSFORMS; ELECTRIC POWER SUPPLIES TO APPARATUS; IMAGE QUALITY;

ARCHITECTURE;

EID: 77957570471     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2025279     Document Type: Article

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