A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 867-870

  Chiang, Jen Shiun ^a   Chiu, Yi Fang ^a   Chang, Teng Hung ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK RATE; CYCLE TIME; DCT/IDCT; DCT/IDCT ARCHITECTURES; DIGITAL IMAGE; HIGH THROUGHPUT; LOOK UP TABLE; MATRIX TRANSPOSITION; REAL TIME IMAGES; ROW-COLUMN; SIMULATION RESULT; STANDARD CELL; TRADITIONAL ARCHITECTURE; VIDEO SIGNAL; VIDEO SYSTEMS; VLSI IMPLEMENTATION;

COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; ELECTRIC BATTERIES; TABLE LOOKUP; THROUGHPUT; VLSI CIRCUITS;

COMPUTER GRAPHICS;

EID: 34548368096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. M. Liou, "Overview of the p×64 kbits/s video coding standard", Commun. ACM, vol. 34, no. 4, pp. 59-63, Apr. 1991.
2. G. K. Wallace, " The JPEG still picture compression standard", Commun. ACM, vol. 34, no. 4, pp. 30-44, Apr. 1991.
3. ISO/IEC DIS 13818-2, "MPEG-2 video", Draft Int. Standard.
4. R. Hopkins, "Digital terrestrial HDTV for North America: the grand alliance HDTV system", IEEE Trans. Consumer Electron., vol. 40, no. 3, pp. 185-198, Aug. 1994.
5. T. C. Chen, "VLSI implementation of a 16×16 DCT", Processing of IEEE ICASSP'88, pp. 1973-1976.
6. W. Li, "A new algorithm to compute the DCT and its inverse", IEEE Trans. Signal Processing, vol. 39, no. 6, pp. 1305-1313, June 1991.
7. C. C. Ju, "A high-throughput DCT/IDCT architecture and design methodology with application to real-Time digital video codec system and associated CAD design", Master Thesis, National Chiao Tung Univ., Taiwan, June 1997.
8. J. Chiang and H. Huang, "Novel architecture for two dimensional high throughput rate real time discrete cosine transform and the VLSI design", International Journal of Electronics, vol. 83, no. 4, Aug. 1997, pp. 519-527.
9. J. Chiang and M. Chiang, " A 2-dimensional DCT/IDCT with overlapped row-column operation", Processing of IEEE ISPACS'98, pp. 580-583.
10. Y. P. Lee, T. H. Chen and L.G. Chen, "A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method", IEEE Trans. Circuit Syst. for Video Technology, vol. 7, no. 3, pp. 459-467, June 1997.
11. M. T. Sun, L. Wu, and M. L. Liou, "A concurrent architecture for VLSI implementation of discrete cosine transform", IEEE Trans. Circuit Syst., vol. CAS-34, no. 8, Aug. 1987.
12. U. Sjostrom, I. Drfilpps, M. Ansorge, and F. Pellandini, "Discrete cosine transform chip for real-time video application", Processing of ISCAS'90, pp. 1620-1623.
13. S. P. Kim, and D. K. Pan, "Highly modular and concurrent 2-d DCT chip", Proceedings of IEEE ISCA'92, pp. 1081-1084.
14. M. H. Sheu, J. Y. Lee, J. F. Wang, A. N. Sueo, and L. Y. Liu, "A high throughput-rate architecture for 8×8 2-D DCT", Proceedings of ICASSP'93, pp. 1587-1590, 1993.
15. T. Miyazaki, "DCT/IDCT processor for HDTV developed with DSP silicon complier", J. VLSI Signal processing, no. 5, pp. 151-158, 1993.
16. H. Fujiwara, "An all-ASIC implementation of a low bit-rate video codec", IEEE Trans. Circuit Syst. for Video Technology, vol. 2, pp. 123-134, June 1992.
17. V. Srinivasan, "VLSI design of high-speed time-recursive 2D DCT/IDCT processor for video application", IEEE Trans. Circuit Syst. for Video Technology, vol. 6, no. 1, pp. 87-96, Feb. 1996.